1. Technical Field
Example embodiments relate to a small form factor solid state image sensor, a method of manufacturing the same, and an imaging apparatus.
2. Related Art
Types of solid-state image sensors that are used for various electronic imaging apparatus like video and still cameras include, for example, a charge-coupled device (CCD) type sensor and a metal-oxide semiconductor (MOS) type sensor. Previously, CCD sensors generally had better sensitivity and image quality than the MOS sensors. However, CCD sensors may require a customized CCD manufacturing process and an additional support device like a driver IC on a circuit board. Further CCD sensors may consume a larger amount of electric power compared to MOS sensors. MOS sensors using complementary MOS (CMOS) technology may consume less power than CCD sensors, and may be manufactured by widely used MOS wafer process.
Solid-state image sensors may also be applied to medical instruments in order to discover a disease or other condition harmful to the health of a patient in the early stages of the condition thereby reducing medical expenses. In these applications, other functionalities, performance and form factors besides sensitivity and image quality should be considered. An endoscope, for example, may require a high image quality solid-state image sensor with a small footprint, which will limit an amount of pain experienced by a patient undergoing endoscopy. However, it may be difficult for the conventional solid-state image sensor to realize a small form factor because of the photo-insensitive portion (dead space) which surrounds an image sensing area on the image sensor. As the dead space increases for a sensor having an image sensing area of a constant size, the diameter of an endoscope-probe may increase.
FIG. 1 (a) shows a prior art MOS sensor. On the MOS sensor 1, a vertical scanning circuit 3, a horizontal scanning circuit 4, and a signal read-out circuit 5 are formed around a rectangular image sensing area 2. A timing pulse generation circuit 6, an analog to digital converter (ADC) circuit 7, a digital image processing circuit 8, and an interface circuit (I/F) 9 are formed on the same MOS sensor 1. The signal read-out circuit 5 includes one or more correlated double sampling circuits CDS to reduce signal noise, for example. Input and/or output buffer circuits 10 and input protection circuits 11 accompanying a contact pad 12 are also integrated on the periphery of the MOS sensor chip 1.
The image sensing area 2 is formed by an array of unit pixels 13. The array includes m pixels horizontally by n pixels vertically. The unit pixel 13 includes optoelectronic conversion device including, for example, a pn-junction photo-diode and a MOS transistor circuit. The unit pixel 13 includes a photo-diode (PD) 14 and the MOS transistor circuit includes an amplifying transistor Tr1, a reset transistor Tr2, and a select transistor Tr3 as shown in the partially enlarged portion of figure of FIG. 1 (a) illustrated in a dashed-line circle. By controlling the reset signal line 16 and the select signal 17, charges stored in the photo-diode 14 are read out through the signal line 19. The signal lines 16 and 17 are connected to, and controlled by, the vertical scanning circuit 3. The signal line 19 connects to the signal read-out circuit 5. Another configuration of the unit pixel 13 is shown in FIG. 1 (b). A charge read transistor Tr4 is formed between the photo-diode 14 and the reset transistor Tr2. The gate electrode of the read transistor Tr4 is connected to the read control signal line 18.
Two types of wiring are defined. One type of wiring is local wiring which runs inside the pixel including, for example, the wiring 15, as shown in FIG. 1 (a). The other type of wiring is global wiring which runs over multiple pixels or across the image sensing area 2. Examples of global wiring include lines 16, 17, 18, and 19. An equivalent circuit diagram of the input protection circuit 11 is shown in FIG. 1 (c). Input protection circuit 11, for example, includes a gate-grounded n-MOS transistor utilizing avalanche-breakdown phenomenon. Input protection circuit 11 includes a series resistor Rr of 3K Ohms and a parallel resistor Rd of 1K to 10K Ohms which limit maximum peak electrical current flow through these components to protect the gate oxide from the electro-static discharge at the gate input terminal of the MOS transistor MOS Tr.
The vertical scanning circuit 3, the horizontal scanning circuit 4 and the signal read-out circuit 5 are located next to vertical and horizontal sides of the image sensing area 2, respectively, which causes misalignment between the center positions of the MOS sensor 1 and the center position of the image sensing area 2 (marked by ‘+’). The alignment of the lens optics with the image sensing area 2 is carefully adjusted to reduce such a misalignment between the center positions of lens optics and image sensing area 2. As used herein, the term ‘image sensing area’ refers to an array of unit pixels. Peripheral circuits and isolation areas in between light-sensitive elements of unit pixels are not light-sensitive. However, though isolation areas in between pixels of the image sensing area 2 are not light-sensitive, as used herein, the term ‘dead space’ refers to peripheral circuits and I/O components including an input protector outside of image sensing area 2, and the term ‘dead space’ does not refer to an isolation area between the pixels of the image sensing area 2. Examples of peripheral circuits that are dead space include the vertical scanning circuit 3, the horizontal scanning circuit 4, the signal read-out circuit 5 and other peripheral circuits including a timing pulse generation circuit 6, an AD converter circuit 7, a digital image processing circuit 8, an interface circuit 9, input and/or output buffer circuits 10, input protection circuits 11, and contact pads 12.
The diagonal length of the image sensing area (the effective image size) used for a mobile-phone and a digital camera is about ⅙ to ½ inch. The effective image size used for medical instruments like an endoscope is about 1/10 inch and still further size reduction may be desirable. As the size of the MOS sensor is decreased, the area of the dead space may become dominant over the area of the image sensing area because the area for the input and/or output buffer circuits, input protection circuits and contact pads are not necessarily proportional to the area for the image sensing area. Consequently, if a surface area of an image sensor is reduced by a certain percentage without reducing a number of pixels, a surface area of an image sensing portion of the chip (e.g., pixel sizes) may become reduced by an even greater percentage. One solution may be to reduce the number of pixels in the image sensor. However, in either case, image qualities such as image resolution or optical sensitivity may be degraded.
The following is a numerical estimation of the dead space versus the image sensing area on a conventional MOS sensor. The estimation is depending on a circuit design rule, fabrication technology and other conditions including a pixel size of the MOS sensor and total number of pixels on the chip. In the case of a 5 mega-pixel, ⅓ inch MOS sensor with a pixel size of 2 square micron-meters, for example, the image sensing area is about 22 mm2. Considering a chip size of 56 mm2, the dead space is approximately 34 mm2, which is larger than the image sensing area of 22 mm2. For example, in the conventional example above, the image sensing area is around 40% of the total area of the face of the chip while the dead space is around 60% of the total area of the face of the chip.
A stacked or three dimensional (3D) sensor structure has been developed. The size of the second semiconductor chip is, however, larger than the first semiconductor chip. For example, in the conventional example provided above, if the dead space portion of the chip, excluding the input and output buffer and input protection circuits, were removed and placed on a second chip, the second chip would have a size of 30 mm2 while the first chip would have a size of only 22 mm2. Consequently, the second chip would be around 36% larger than the first chip.
As for the stacked sensor structure, input protection circuits may be required for each input terminal between the chips in addition to externally exposed input terminals, otherwise MOS transistor input gate insulating material may be damaged from an electro-static discharge (ESD).
The external form of the MOS sensor and the image sensing area are rectangles or squares same as other semiconductor chips including, for example, memory and logic ICs. An optical image formed through the lens system is neither a rectangle nor a square but a circle. The MOS sensor having a diagonal length that is the same as the above-referenced optical circle would not cover the entire optical image. In an alternative case where a larger MOS sensor is used that has an image sensing area that covers an entirety of a projected circle image corresponding to the above-referenced optical circle, the image sensing area of the four corners of the larger MOS sensor are outside the projected image and not utilized for image sensing.
The horizontal scanning circuits and vertical scanning circuit that are composed of a series of unit circuits including, for example, a shift register circuit, are arranged in a row and column direction so as to be aligned with the arrangement of pixels in horizontal and vertical directions respectively. In the stacked type sensor, however, peripheral circuits like the horizontal and the vertical scanning circuits are integrated on the second semiconductor chip. Further, according to example embodiments, control signal lines to, and output signal lines from, each pixel may be routed between the first and second semiconductor chips.
As is shown in FIG. 1 (a), the vertical scanning circuit may have a series of shift registers which correspond to each horizontal global wiring outside of the image sensing area. Straight and same pitch global lines may be routed with the pixel array, and such routing which may suppress fixed pattern noise due to signal delay non-uniformity. With respect to a stacked structure, the first semiconductor chip may be layered on the larger size of the second semiconductor chip in order to keep the above-mentioned same routing pitch of the global lines or shift register layout pattern. The MOS sensor size, in such a case, may be dependent on the larger size of the second semiconductor chip.